Please use this identifier to cite or link to this item:https://hdl.handle.net/20.500.12259/56551
Type of publication: research article
Type of publication (PDB): Straipsnis Clarivate Analytics Web of Science / Article in Clarivate Analytics Web of Science (S1)
Field of Science: Informatika / Informatics (N009);Informatikos inžinerija / Informatics engineering (T007)
Author(s): Man, Ka Lok;Lei, Chi-Un;Kapoor, Hemangee K;Krilavičius, Tomas;Ma, Jieming;Zhang, Nan
Title: PAFSV: a formal framework for specification and analysis of SystemVerilog
Is part of: Computing and informatics. Bratislava : Slovak Academy of Sciences, Institute of Informatics, 2016, Vol. 35, iss. 1
Extent: p. 143-176
Date: 2016
Keywords: PAFSV;Verilog;Procesų algebros;Formali semantika;Grandinių verifikavimas;PAFSV;SystemVerilog;Process algebras;Formal semantics;Circuit verification
Abstract: We develop a process algebraic framework PAFSV for the formal specification and analysis of IEEE 1800TM SystemVerilog designs. The formal semantics of PAFSV is defined by means of deduction rules that associate a time transition system with a PAFSV process. A set of properties of PAFSV is presented for a notion of bisimilarity. PAFSV may be regarded as the formal language of a significant subset of IEEE 1800TM SystemVerilog. To show that PAFSV is useful for the formal specification and analysis of IEEE 1800TM SystemVerilog designs, we illustrate the use of PAFSV with a multiplexer, a synchronous reset D flip-flop and an arbiter
Internet: http://cai.type.sk/content/2016/1/pafsv-a-formal-framework-for-specification-and-analysis-of-systemverilog/
Affiliation(s): Baltijos pažangių technologijų institutas, Vilnius
Taikomosios informatikos katedra
Vytauto Didžiojo universitetas
Appears in Collections:Universiteto mokslo publikacijos / University Research Publications

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